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Rochester Electronics lists 74S288AV as a 256-bit, 32-word by 8-bit TTL programmable read-only memory and as an alternate for 27S19AJC. The exact AV package and programmed contents must be confirmed for any replacement; this page does not imply a blank PROM is interchangeable with an already programmed one.
The 74S288 family stores a one-time-programmed 8-bit output word at each of 32 addresses. Rochester supplies the 74S288AV for legacy maintenance where electrically and mechanically compatible OTP PROMs are needed. The local catalog has no package designation, and available secondary listings do not constitute a controlled package drawing.
The family uses five address inputs to select one of 32 eight-bit words. An enable input controls output availability. As a bipolar fuse PROM, it must be programmed using an approved procedure and programmer; it is not an electrically erasable memory. Verify output polarity, enable behavior and timing from the exact Rochester-controlled data sheet before replacing a board device.
The catalog package field is blank. A Rochester-referenced engineering directory classifies the AV variant as PLCC20, whereas N and AN variants are listed as PDIP16. The exact 74S288AV mechanical drawing and pin map were not obtained. A 20-PLCC is therefore a candidate requiring manufacturer confirmation, not an approved footprint. The local 20-PLCC JPG and package registry are missing.

Family-level signals include address inputs, eight parallel data outputs, enable/control, 5 V supply and ground. The candidate PLCC20 pin positions must not be inferred from a PDIP16 family diagram. Verify the exact 74S288AV ball/lead assignment and programming pins using Rochester documentation.
| Exact order code | 74S288AV |
|---|---|
| Listed manufacturer | Rochester Electronics |
| Memory type | Bipolar TTL PROM |
| Capacity | 256 bits |
| Organization | 32 x 8 |
| Address width | 5 bits |
| Data width | 8 bits |
| Programming | One-time; verify approved method |
| Supply class | 5 V TTL family; exact limits to verify |
| Rochester cross-reference | 27S19AJC; not approved without checks |
| Exact package | Unconfirmed; PLCC20 candidate |
| Local package JPG | Missing |
Only family-level memory architecture is established here; exact AV timing, outputs, programming and package require controlled documentation.
The database also contains 74S288AN and 74S288N. These are family comparisons only: distributor package classifications suggest DIP versus candidate PLCC for AV. Even a pin-compatible PROM requires the same programmed data image, output polarity and speed. Rochester's 27S19AJC cross-reference is not a substitute for such validation.
Rochester's product-family description identifies the 74S288 as a 32 x 8, 256-bit TTL PROM. Historical Signetics and Texas Instruments manufacturer-authored family material corroborates the generic 74S288 memory architecture. No current Rochester-controlled 74S288AV electrical, programming and mechanical data sheet was retrieved; obtain it before technical release.
Inspect device markings, lot and date code, packaging and especially the programmed image. The local catalog lists 11,197 units at USD 9.64, minimum quantity 11, no tiers. Current exact-code external listings diverge: an indexed Rochester offer reports 13,245 units at USD 25.13 for one and USD 23.62 for 100; a separate seller reports 10,000 at USD 12.3065 for one and USD 11.5681 for ten. These listings are unverified seller claims, and the catalog stock/price conflict requires procurement review. Do not change catalog values without authorization.
It is organized as 32 words of 8 bits, or 256 bits.
No. The application-specific data image must be programmed and verified.
No. This is a secondary-source candidate; the controlled Rochester drawing is needed.
No. Exact-code distributor offers differ materially.
Obtain the manufacturer-controlled AV data sheet, package outline, programming algorithm and known-good memory image. Missing package JPG/registry and unresolved distributor stock/pricing prohibit publication. Keep this record in manual review with noindex until all checks pass.
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