Unit Price:$14.68
Ext Price:$14.68



PCI11101/MXX from Microchip Technology combines PCIe switching, a single-port USB 3.2 Gen 2 host controller, and programmable I/O for embedded expansion designs.
Technical details follow Microchip's PCI11101 product brief and hardware checklist. Stock and price observations refer to the exact DigiKey order code.
The PCI11101 integrates a four-lane upstream PCIe port and a two-lane downstream port, each specified at up to 8 GT/s per lane. Its xHCI-compliant USB 3.2 Gen 2 host controller provides one 10 Gbps USB port and USB 2.0 high-, full-, and low-speed support. A programmable pin multiplexer makes serial and general-purpose I/O available to the system.
Combines PCIe switching and a USB 3.2 Gen 2 host function in one IC.
Four upstream and two downstream PCIe lanes support compact expansion topologies.
A configurable pin multiplexer supports GPIO and serial peripheral functions.
The /MXX tray order code uses a 132-pin DRQFN package.
Four-lane upstream and two-lane downstream physical interfaces, up to 8 GT/s per lane.
One xHCI USB 3.2 Gen 2 port, with USB 2.0 HS/FS/LS operation.
Programmable GPIO, UART, SPI and SMBus functions; use the hardware checklist for configuration straps.
A 25 MHz crystal or clock and a PCIe reference clock are required externally.
The exact PCI11101/MXX order code is commercial-temperature, tray packed, and supplied in a 132-pin DRQFN package. DigiKey describes a 132-VFQFN dual-row exposed-pad case and a 132-DRQFN 11 mm x 11 mm supplier package.
Expected library path: /upload/package/132-VFQFN-Dual-Rows-Exposed-Pad.jpg
This is a functional guide, not a numbered pinout. Use the latest Microchip package drawing and data sheet for layout.
| Device class | PCIe switch with integrated USB host |
|---|---|
| Upstream PCIe | 4 lanes, up to 8 GT/s per lane |
| Downstream PCIe | 2 lanes, up to 8 GT/s per lane |
| USB controller | One USB 3.2 Gen 2 xHCI host port, 10 Gbps |
| Other USB modes | USB 2.0 high/full/low speed |
| Programmable functions | GPIO, UART, SPI and SMBus |
| External clocks | 25 MHz crystal or clock plus PCIe reference clock |
| Power rails | 3.3 V and 1.1 V |
| Temperature grade | Commercial, 0 C to +70 C |
| Package | 132-pin DRQFN, 11 mm x 11 mm |
| Packaging | Tray |
PCI11101-I/MXX is an API-confirmed internal industrial-temperature variant. The temperature suffix differs; verify all electrical, firmware, qualification, marking, and supply requirements before considering substitution. A shared family name does not establish drop-in compatibility.
Microchip lists PCI11101 as an in-production PCIe peripheral. Its product brief documents the PCIe topology, USB host capability, operating grades, and /MXX ordering code; the hardware checklist covers integration details.
Adds a downstream PCIe link and USB host connectivity to a host design.
Supports high-bandwidth peripheral attachment in compact embedded equipment.
Provides PCIe, USB, and programmable I/O resources for platform integration.
Confirm the complete PCI11101/MXX order code, tray label, package marking, lot traceability, moisture handling, and authorized-channel records before assembly. Do not infer the industrial grade from package appearance.
A PCIe switch, one USB 3.2 Gen 2 host controller, and programmable I/O.
Four upstream and two downstream lanes, each up to 8 GT/s.
The non-I tray order code is commercial, 0 C to +70 C.
No. The registered local JPG is missing, so publication is blocked.
Use the current Microchip data sheet, product brief and hardware checklist for pin numbers, absolute ratings, clocks, power, PCIe and USB routing, reset, thermal design, configuration, and production approval. Distributor information is for sourcing and does not replace manufacturer limits.
The following parts include "PCI11101/MXX" in Silicon Labs PCI11101/MXX.
The following parts are popular search parts in Test and Measurement.
| Qty. | Unit Price | Ext. Price |
| 1+ | $14.68 | $14.68 |
| 25+ | $12.23 | $305.75 |
| 100+ | $11.81 | $1181.00 |