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Microchip Technology PCI11101/MXX

Part No.:
PCI11101/MXX
Manufacturer:
Microchip Technology
Category:
Specialized ICs
Package:
132-VFQFN Dual Rows, Exposed Pad
Description:
IC ANALOG SWITCHES 132DRQFN
Quantity:

Unit Price:$14.68

Ext Price:$14.68

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Product Details

PCI11101/MXX - PCIe Switch with USB 3.2 Gen 2 Host and Programmable I/O

PCI11101/MXX from Microchip Technology combines PCIe switching, a single-port USB 3.2 Gen 2 host controller, and programmable I/O for embedded expansion designs.

Technical details follow Microchip's PCI11101 product brief and hardware checklist. Stock and price observations refer to the exact DigiKey order code.

Overview

The PCI11101 integrates a four-lane upstream PCIe port and a two-lane downstream port, each specified at up to 8 GT/s per lane. Its xHCI-compliant USB 3.2 Gen 2 host controller provides one 10 Gbps USB port and USB 2.0 high-, full-, and low-speed support. A programmable pin multiplexer makes serial and general-purpose I/O available to the system.

Design focus: Review the manufacturer's clock, power-rail, reset, PCIe routing, USB Vbus and overcurrent, and configuration guidance before schematic or PCB release.

Key Advantages

Consolidated connectivity

Combines PCIe switching and a USB 3.2 Gen 2 host function in one IC.

Flexible lane layout

Four upstream and two downstream PCIe lanes support compact expansion topologies.

Programmable I/O

A configurable pin multiplexer supports GPIO and serial peripheral functions.

Documented package

The /MXX tray order code uses a 132-pin DRQFN package.

Feature Summary

PCIe switching

Four-lane upstream and two-lane downstream physical interfaces, up to 8 GT/s per lane.

USB host

One xHCI USB 3.2 Gen 2 port, with USB 2.0 HS/FS/LS operation.

I/O and configuration

Programmable GPIO, UART, SPI and SMBus functions; use the hardware checklist for configuration straps.

Clocking

A 25 MHz crystal or clock and a PCIe reference clock are required externally.

Package & Footprint

The exact PCI11101/MXX order code is commercial-temperature, tray packed, and supplied in a 132-pin DRQFN package. DigiKey describes a 132-VFQFN dual-row exposed-pad case and a 132-DRQFN 11 mm x 11 mm supplier package.

Package-image status: The package is registered, but the required local JPG is absent. This page must remain in review until a verified JPG is available.

Expected library path: /upload/package/132-VFQFN-Dual-Rows-Exposed-Pad.jpg

Functional Connections

PCIe upstream
Up to four differential lanes to the host.
PCIe downstream
Up to two differential lanes to an expansion device.
USB host
USB 3.2 Gen 2 and USB 2.0 signals, Vbus control and overcurrent sensing.
Clock and reset
25 MHz device clock, PCIe reference clock and reset/power sequencing.
Programmable I/O
GPIO, UART, SPI and SMBus functions according to pin-mux configuration.
Power and pad
3.3 V and 1.1 V supply domains and exposed-pad connection.

This is a functional guide, not a numbered pinout. Use the latest Microchip package drawing and data sheet for layout.

Key Specifications

Device classPCIe switch with integrated USB host
Upstream PCIe4 lanes, up to 8 GT/s per lane
Downstream PCIe2 lanes, up to 8 GT/s per lane
USB controllerOne USB 3.2 Gen 2 xHCI host port, 10 Gbps
Other USB modesUSB 2.0 high/full/low speed
Programmable functionsGPIO, UART, SPI and SMBus
External clocks25 MHz crystal or clock plus PCIe reference clock
Power rails3.3 V and 1.1 V
Temperature gradeCommercial, 0 C to +70 C
Package132-pin DRQFN, 11 mm x 11 mm
PackagingTray

Replacement Considerations

PCI11101-I/MXX is an API-confirmed internal industrial-temperature variant. The temperature suffix differs; verify all electrical, firmware, qualification, marking, and supply requirements before considering substitution. A shared family name does not establish drop-in compatibility.

Manufacturer Information

Microchip lists PCI11101 as an in-production PCIe peripheral. Its product brief documents the PCIe topology, USB host capability, operating grades, and /MXX ordering code; the hardware checklist covers integration details.

Applications

Embedded PCIe expansion

Adds a downstream PCIe link and USB host connectivity to a host design.

Vision and machine systems

Supports high-bandwidth peripheral attachment in compact embedded equipment.

Server management subsystems

Provides PCIe, USB, and programmable I/O resources for platform integration.

Quality & Authenticity

Confirm the complete PCI11101/MXX order code, tray label, package marking, lot traceability, moisture handling, and authorized-channel records before assembly. Do not infer the industrial grade from package appearance.

FAQ

What does PCI11101 integrate?

A PCIe switch, one USB 3.2 Gen 2 host controller, and programmable I/O.

What is the PCIe topology?

Four upstream and two downstream lanes, each up to 8 GT/s.

What temperature grade is /MXX?

The non-I tray order code is commercial, 0 C to +70 C.

Is the package JPG ready?

No. The registered local JPG is missing, so publication is blocked.

Engineering Notice

Use the current Microchip data sheet, product brief and hardware checklist for pin numbers, absolute ratings, clocks, power, PCIe and USB routing, reset, thermal design, configuration, and production approval. Distributor information is for sourcing and does not replace manufacturer limits.

PCI11101/MXX Information

  • Specifications
  • Tags
Product attributes
Attribute value
Manufacturer:
Microchip Technology
Series:
-
Package/Case:
132-VFQFN Dual Rows, Exposed Pad
Packaging:
Tray
Product Status:
Active
Programmable:
-
Type:
Analog Switches
Applications:
-
Mounting Type:
Surface Mount
Supplier Device Package:
132-DRQFN (11x11)
Grade:
-
Qualification:
-
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