Analog Devices Inc. LTC4213CDDB#TRPBF

The LTC4213 monitors the voltage between SENSEP and SENSEN across an external N-channel MOSFET, eliminating a discrete series sense resistor. An internal charge pump drives the gate. Separate slow and fast comparators provide two levels of overcurrent protection, while ON controls startup and fault reset and READY indicates an armed, conducting switch.

LCDChip registers 8-WFDFN Exposed Pad. The manufacturer's exact-order table describes LTC4213CDDB#TRPBF as an eight-lead 3 mm × 2 mm plastic DFN (DDB) with exposed pad and tape-and-reel supply. The exposed pad may be left open or connected to device ground according to the data sheet; use the DDB land pattern, not the TSOT-23 footprint.

Layout checks

• Confirm DDB orientation and 3 mm × 2 mm body dimensions.
• Route SENSEP and SENSEN to opposite ends of the external MOSFET.
• Check gate-loop layout and fault-current thermal limits.

The expected local JPG is absent and its production URL returns HTTP 404. Keep this draft unpublished until the correct image is restored and inspected.

For the DDB DFN only: pin 1 READY is an open-drain armed-state output; pin 2 ON controls enable and reset; pin 3 ISEL selects the trip level; pin 4 GND is device ground; pin 5 GATE drives the external N-channel MOSFET; pin 6 SENSEN connects to its source; pin 7 SENSEP connects to its drain; and pin 8 VCC is the 2.3 V to 6 V bias input. Exposed pad 9 may remain open or connect to ground. The TSOT-23 variant has a different pin mapping.

The threshold and timing figures are condition-dependent; use the full min/typ/max electrical tables for design limits.

Do not assume that other LTC4213 grades or packages are interchangeable. The I-grade DDB order code has a wider temperature range, but grade selection, ordering suffix and actual supplied part must be checked. TSOT-23 options use a different footprint and pin assignment. Other circuit breakers can differ in sense method, trip thresholds, gate-drive behavior and reset logic. No unverified internal alternative is linked.

Analog Devices' LTC4213 No RSENSE Electronic Circuit Breaker data sheet Rev. A provides the exact C-grade DDB ordering row, pin functions, operating conditions and protection characteristics. Check the latest controlled revision and package drawing during design release.

Check device marking, lot traceability, DDB body and pad geometry, and the shipped C-grade order code. Validate the three ISEL configurations, ON reset, READY status, gate discharge and both fault paths on the target board. Characterize the external FET over temperature.

Confirm MOSFET RDS(ON) variation, safe operating area, thermal response, trip thresholds, DDB footprint and system fault behavior using the current manufacturer documentation. Restore and visually verify the production package JPG before formal publication.