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KSZ8695PX is the lead-free standard-temperature version of Micrel's KS8695PX gateway system-on-chip, documented by Microchip. It combines an ARM9 processor, five 10/100 Ethernet MAC/PHY ports, a nonblocking switch, PCI and external-memory control in a 289-pin PBGA.
The manufacturer's Rev. 1.3 ordering table identifies the exact KSZ8695PX code, 0°C to +70°C grade and 289-pin PBGA. The site's “289-BGA” catalog label is generic; the PX-specific ball and package drawings govern design.
KSZ8695PX targets residential and small-office broadband gateways. One WAN and four LAN Fast Ethernet MAC/PHY channels connect to an integrated switch, while the ARM9 CPU executes gateway software. The 32-bit PCI interface and programmable 8/16/32-bit external-memory path support expansion without separate CPU and switch chips.
ARM9 processing, five Ethernet transceivers/MACs and switch functions are integrated.
XceleRouter provides checksum assistance and DMA for WAN/LAN packet transfers.
33-MHz 32-bit PCI and shared external-memory/I/O interfaces support companion hardware.
VLAN, QoS, IGMP snooping, port mirroring and rate limiting are documented switch capabilities.
Up to 166 MHz with 8 KB instruction cache, 8 KB data cache and an MMU.
Five 10/100 transceivers and MACs, arranged as one WAN and four LAN ports.
32-bit, 33-MHz PCI 2.1 interface with an arbiter supporting one external master.
Sixteen GPIOs, two 32-bit timers including a watchdog, UART, interrupts and JTAG.
The KS8695PX Rev. 1.3 data sheet specifies a 289-pin plastic ball-grid array with a nominal 19 mm × 19 mm body. The product API and workbook registry use the generic “289-BGA” label. Retain that catalog designation but use the manufacturer's PX-specific ball map, 1.0-mm pitch and mechanical drawing to release the PCB footprint.

The registered local JPG is absent and the production JPG returns HTTP 404, so the package visual cannot be verified and publication is blocked.
The 289-ball interface groups Ethernet PHY/MAC ports, PCI, external memory and I/O, power, clocks, reset and debug. Use the PX data sheet's complete signal and ball tables instead of a generic BGA or KSZ8695P pinout.
The functional groups above are not a ball-by-ball pinout. Confirm the latest manufacturer revision and recommended reset circuit.
| Exact ordering code | KSZ8695PX, lead-free standard grade |
|---|---|
| Function | Multi-port PCI Ethernet gateway SoC |
| Processor | ARM9 core, up to 166 MHz |
| CPU caches | 8 KB instruction and 8 KB data |
| Ethernet | Five 10/100 MAC/PHY ports |
| Switch | Nonblocking five-port engine; 64 KB frame-buffer SRAM |
| PCI interface | 32-bit, 33 MHz; one external master via integrated arbiter |
| External data path | Programmable 8/16/32-bit |
| Memory space | Up to 64 MB total |
| GPIO | 16 general-purpose lines |
| Supply domains | 1.8 V core/RX; 3.3 V I/O/TX |
| Operating temperature | 0°C to +70°C |
| Package | 289-pin PBGA, nominal 19 mm × 19 mm |
Summary values are from Micrel KS8695PX Rev. 1.3, hosted by Microchip. Verify full electrical and timing conditions before design use.
KSZ8695P and KSZ8695PX are distinct order codes; do not assume that their PCI arbitration, pin maps or software interfaces match. For any alternative, compare the PBGA ball map, Ethernet features, power domains, reset behavior, firmware, PCI and memory timing. No internal alternative is linked because exact API-confirmed compatibility was not established.
The KS8695PX platform was documented by Micrel; the Rev. 1.3 data sheet is hosted by Microchip Technology. Its ordering table pairs standard KS8695PX with lead-free KSZ8695PX and identifies 0°C to +70°C, 289-pin PBGA. Use the PX document when checking exact features and layout.
Residential and small-office equipment integrating routing and switching.
PCI-expanded access points, mesh nodes and wireless gateways.
Multi-port firewall, VPN and managed customer-premises systems.
Connected storage, multimedia and digital-audio network devices.
Confirm the exact KSZ8695PX marking, lead-free suffix, package condition, ball integrity, lot traceability and ESD handling. Compare received devices and the board footprint with the manufacturer PX package drawing. Do not substitute a P or other KS8695-family device merely because the catalog BGA label matches.
Yes. The manufacturer specifies an ARM9 core with caches and an MMU.
Five 10/100 Ethernet MAC/PHY ports: one WAN and four LAN.
No. They are separate order codes and must be checked against their respective data sheets.
Use the exact KS8695PX data sheet for ball assignment, reset design, clocking, power sequence, PCI and memory interfaces, Ethernet magnetics and firmware support. The generic “289-BGA” catalog description needs PBGA drawing verification, and the registered production JPG is missing. Keep the page unpublished until the package visual and all final checks pass.
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