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Harris Corporation HSP45240GC-40 is a 24-bit programmable address sequencer in a 68-lead ceramic PGA, package drawing G68.A. The manufacturer-authored Intersil HSP45240 ordering table identifies this exact 0 to +70 C, -40 speed-grade variant.
Use the GC PGA bottom-view coordinate map and -40 timing column, not the JC PLCC numbered pinout or the faster -50 grade.
The HSP45240 creates block-oriented memory-address sequences for DSP and image-processing work. A 24-by-24 crosspoint switch remaps output address bits for patterns such as FFT bit reversal. The same device can be configured as two independent 12-bit sequencers, with programmable delay on twelve outputs and a processor interface for setup.
Twenty-four-bit block sequencing for memory-oriented algorithms.
Two independent twelve-bit address streams when configured.
Twenty-four-by-twenty-four mapping supports nonsequential output patterns.
Programmable delay on twelve address outputs helps align stages.
D0-D6, CS, A0 and WR form a microprocessor configuration interface.
STARTIN and STARTOUT support coordinated sequencing across devices.
ADDVAL, BUSY, BLOCKDONE and DONE report sequence progress.
OEH and OEL control upper and lower output groups separately.
The 1997 manufacturer-authored ordering table specifies HSP45240GC-40 as a 68-lead PGA, drawing G68.A. The catalog's 68-BCPGA matches the local registered normalized package name, recorded in workbook row 713 in the immediately preceding batch. The PGA bottom view differs from the PLCC top view; verify ceramic body size, keying, pin grid and socket against G68.A and the shipped lot.

The registered 68-BCPGA JPG is absent locally; keep the page unpublished.
The manufacturer's PGA bottom view identifies D0-D6, CS, A0 and WR for programming; CLK and RST for timing and reset; STARTIN, STARTOUT and DLYBLK for sequence control; ADDVAL, BUSY, BLOCKDONE and DONE for status; and OUT0-OUT23 with OEH/OEL for address outputs. Use the letter-number PGA grid in the controlled diagram. A PLCC pin number cannot be transferred to this package.
D0-D6, CS, A0 and WR.
CLK, RST, STARTIN, STARTOUT and DLYBLK.
ADDVAL, BUSY, BLOCKDONE and DONE.
OUT0-OUT23 with OEH and OEL.
Confirm all G68.A coordinates and the supplied lot's orientation before schematic release.
| Exact order code | HSP45240GC-40 |
|---|---|
| Original maker | Harris Corporation / later Intersil documentation |
| Function | Programmable address sequencer |
| Speed grade | -40, 40 MHz class |
| Minimum clock period | 25 ns, -40 AC column, VCC 5.0 V ±5%, TA 0 to +70 C |
| Minimum clock high/low | 10 ns each under the same -40 AC conditions |
| Address width | 24 bits or two 12-bit streams |
| Crosspoint switch | 24-by-24 |
| Programmable output delay | 12 output bits |
| Supply | 5.0 V nominal family, check full DC limits |
| Temperature range | 0 to +70 C exact ordering row |
| Package | 68-lead PGA G68.A; catalog 68-BCPGA |
Timing limits apply only under the manufacturer's stated loading and test conditions.
No LCDChip internal alternate is linked or approved. Harris listed GC-33 and GC-50 PGA speed grades and JC-40 PLCC. GC-33 is slower; GC-50 needs electrical and procurement checks; JC-40 has a different package. Validate programming behavior, reset, output loading, clock margin, G68.A grid and temperature grade before any substitution.
Harris' historical product guide and the 1997 Intersil HSP45240 data sheet list exact GC-40 in a commercial 68-lead PGA, G68.A. The later Renesas-hosted family data sheet includes -40 electrical timing but presents the JC PLCC package in its reduced ordering table. Keep the original GC package document with the device's traceability records.
Bit reversal and mapped memory traversal.
Pan and zoom address generation.
One- and two-dimensional data-block sequencing.
Coordinated reads and writes in legacy DSP systems.
Check the exact Harris GC-40 marking, date/lot code, original ceramic PGA and pin condition. Catalog stock and base price are separate commercial fields. Indexed exact-code sellers disagree on stock and quantity pricing; secure a dated authorized quote and confirm lot provenance before updating inventory terms or publishing.
No. Its AC column specifies a 25 ns minimum clock period, corresponding to the 40 MHz class.
No direct package substitution is established; GC is PGA and JC is PLCC.
Yes, family documentation describes two independent 12-bit sequencers.
No. The registered 68-BCPGA JPG is missing locally.
Keep this item in manual review. Restore the 68-BCPGA JPG, verify G68.A coordinates and the supplied lot, reconcile exact-code authorized stock and tier pricing, and repeat database and rendered-page checks. No release or drop-in substitution is approved.
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