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A dual-card-port SD/SDIO/MMC signal multiplexer with bidirectional data and command paths, buffered clock routing, independent card-port supplies, and high-impedance disable control.
The exact FSSD06UMX code and 24-lead ultrathin molded leadless package are documented by Fairchild/onsemi.
FSSD06UMX routes one host SD/SDIO or MMC interface to either of two card-side ports. DAT[3:0] and CMD are bidirectional paths, while CLK is distributed through a unidirectional buffered path. Separate VDDC1 and VDDC2 rails support card-port voltage domains, and VDDH supplies the host-side interface.
One host interface can be switched between two SD/SDIO/MMC connections.
CMD and four-bit DAT buses transfer in either direction as required by the protocol.
VDDH, VDDC1, and VDDC2 accommodate host and card-side voltage domains described by the datasheet.
Active-high disable places signal ports in high impedance while inactive clock outputs are pulled high internally.
FSSD06UMX uses a 24-lead ultrathin molded leadless package (UMLP). The site registry lists the original product package as 24-UFQFN.

The expected production JPG is not currently available; publication must wait for image verification.
VDDH powers the host ASIC interface domain.
VDDC1 and VDDC2 power the two peripheral-card interface domains.
/OE is active low; S selects card port 1 or 2.
DAT[3:0], CMD, and CLK connect to the host interface.
1DAT[3:0], 1CMD, and 1CLK connect to the first card interface.
2DAT[3:0], 2CMD, and 2CLK connect to the second card interface.
When /OE is high, all signal ports are high impedance and both card clock outputs are held high through internal pull-ups.
| Ordering code | FSSD06UMX |
|---|---|
| Function | SD/SDIO/MMC two-port multiplexer |
| Data bus | Four bidirectional data lines |
| Command path | Bidirectional |
| Clock path | Unidirectional buffered |
| Host supply | VDDH |
| Card supplies | VDDC1 and VDDC2 |
| Operating temperature | -40 °C to +85 °C |
| Package | 24-lead ultrathin molded leadless package (UMLP) |
| Packing | Tape and reel |
Use the official datasheet for guaranteed voltage ranges, resistance, capacitance, propagation delay, leakage, and timing limits.
No drop-in replacement is asserted. Compare supply-domain ranges, SD/SDIO/MMC signaling direction, clock buffering, internal pull-ups, on-resistance, bandwidth, off isolation, control truth table, power-off behavior, UMLP footprint, and pin assignment.
FSSD06 was introduced by Fairchild Semiconductor and is now supported through onsemi documentation. Primary source: the official FSSD06 datasheet.
Verify the FSSD06UMX ordering code, package marking, 24-lead UMLP geometry, pin-one mark, reel label, lot/date code, moisture handling, solderability, and traceability. Inspect the leadless underside for oxidation, reballing, residue, or mechanical damage.
It switches four SD data lines, the command line, and the clock path between one host and either of two card ports.
The signal ports enter high impedance while the two card-side clock outputs are pulled high internally.
VDDH supplies the host domain; VDDC1 and VDDC2 supply the two card-port domains.
This page is an engineering selection aid. Validate the latest official datasheet, package drawing, voltage-domain sequencing, SD timing, signal integrity, and production footprint before release.
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