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DS3182 is the dual-port member of the Maxim Integrated DS3181-DS3184 family. It combines DS3/E3 physical-layer processing and line interface functions with ATM-cell and packet-oriented system interfaces.
Analog Devices lists the family product as obsolete. Confirm the exact ordering code, mechanical drawing and available lot before a maintenance build.
Each DS3182 port is independently configurable for DS3 or E3 operation. Integrated line interface units provide clock and data recovery, transmit pulse shaping and jitter attenuation. The device connects high-rate serial lines to an ATM or packet processor through selectable parallel interfaces.
Configure each channel for a DS3 or E3 line to suit mixed network equipment.
Line-side clock recovery and transmit waveshaping reduce external circuitry.
UTOPIA and POS-PHY modes connect to ATM and packet processing logic.
Jitter attenuation is configurable on the transmit or receive path.
Supports either line format on each port with integrated receive and transmit processing.
Supports ATM-cell and HDLC packet transport according to the selected mode.
The host-side interface can use 8-, 16- or 32-bit data paths as configured.
The manufacturer's feature summary describes 75-ohm coax operation up to 380 m for DS3 or 440 m for E3 under its stated conditions.
DS3182 is listed in the manufacturer ordering table as a 400-ball TE-PBGA with a 27 mm by 27 mm body and 1.27 mm ball pitch. The catalog calls it 400-BBGA. The package workbook has a 400-BBGA registration at row 870, but its referenced local JPG is absent. Verify the manufacturer ball map, land pattern and thermal requirements before using a generic BBGA drawing.

The registered local JPG is missing and publication remains blocked.
Use the controlled Rev. 3 ball assignment and application circuits for exact connections. The groups below describe the functional interface and are not a substitute for the manufacturer ball map.
Separate transmit and receive line connections serve each of the two DS3/E3 ports through the recommended transformer arrangement.
Parallel UTOPIA or POS-PHY data, clock and control signals connect to the ATM or packet processor.
Clock, reset and configuration inputs establish the selected line and host operating mode.
Observe every specified supply and ground ball and the data-sheet decoupling guidance.
| Exact order code | DS3182 |
|---|---|
| Manufacturer | Maxim Integrated, now Analog Devices |
| Function | Dual DS3/E3 ATM and packet PHY with integrated LIUs |
| Port count | 2, independently configured |
| Line standards | DS3 or E3 per port |
| System bus | UTOPIA Level 2/3 or POS-PHY Level 2/3, SPI-3 modes |
| Bus width | 8, 16 or 32 bits by mode |
| Traffic formats | ATM cells and HDLC packets |
| Operating temperature | 0 °C to +70 °C for DS3182 ordering row |
| Package | 400-ball TE-PBGA; catalog 400-BBGA |
| Body and pitch | 27 mm by 27 mm; 1.27 mm pitch |
| Product status | Obsolete per Analog Devices |
Mode-dependent timing, electrical limits and line-interface circuitry must be checked against the Rev. 3 data sheet.
The DS3181, DS3183 and DS3184 are different port-count family members, not automatic board-level replacements. DS3182N is a different temperature-grade ordering code, and a + suffix denotes a lead-free option. Verify ball assignment, host-bus configuration, line transformer network, clocking, firmware and qualification before any substitution. No unverified internal alternative links are included.
Analog Devices hosts the former Maxim Integrated DS3182 product page and the Rev. 3 DS3181-DS3184 data sheet. The exact DS3182 ordering row establishes commercial-temperature operation and the 400-ball TE-PBGA outline. ADI marks the product obsolete, so procurement requires lot and lifecycle checks.
Dual DS3/E3 line termination in established ATM access equipment.
Packet PHY connectivity for compatible transport and adaptation designs.
Maintenance of legacy wide-area network line cards.
DS3/E3 traffic generation, reception and diagnostics in qualified systems.
For obsolete stock, request original manufacturer traceability, lot/date code, moisture-sensitive handling records and package inspection. Check BGA ball condition, evidence of rework and electrical operation in the target DS3/E3 mode. Stock and price listings are time-sensitive and do not establish traceability.
It provides two independently configurable DS3/E3 ports.
No. The N suffix is the extended-temperature variant; confirm the exact code on the device.
The DS3182 ordering row specifies a 400-ball TE-PBGA measuring 27 mm by 27 mm at 1.27 mm pitch.
No. The registered 400-BBGA JPG is missing from the local package directory.
This record requires human review of the exact ordering code, current qualified distributor stock and tier prices, local package JPG, footprint and lot provenance. Keep it unpublished until every source, inventory, image and page check passes and a reviewer approves publication.
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