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Analog Devices Inc./Maxim Integrated DS3162

Part No.:
DS3162
Manufacturer:
Analog Devices Inc./Maxim Integrated
Category:
Specialized ICs
Package:
400-BBGA
Description:
IC ATM/PACKET PHYS 400PBGA
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Product Details

DS3162 — Dual-Port DS3/E3 ATM and Packet PHY

The Maxim Integrated DS3162, documented by Analog Devices, is a dual-port ATM-cell and HDLC-packet physical-layer processor for DS3, E3 and STS-1-class digital transport applications. It combines two configurable cell/packet processors with DS3/E3 framing functions and a selectable system-side bus interface.

The unsuffixed DS3162 is the 0°C to +70°C, 400-ball TE-PBGA ordering option. Verify the exact device revision and published errata before board replacement.

Overview

The DS3162 maps and demaps ATM cells or HDLC packets between a system-side bus and two independently configurable digital line ports. Each port can be set for supported DS3, E3 or clear-channel operation. On-chip framing and formatting functions reduce the external digital logic required in a telecom interface, while the host configures operating modes and monitors status through the microprocessor interface.

This is a PHY/framer device. Validate the required external line-interface circuitry and clock architecture against the complete manufacturer data sheet; do not infer an integrated analog line interface from the family name.

Key Advantages

Two independent ports

Separate port configuration supports mixed cell and packet traffic where the chosen bus mode allows it.

Integrated framing

On-chip DS3 and E3 framers support the documented framing formats and clear-channel paths.

System-bus flexibility

UTOPIA and POS-PHY interface choices enable integration with ATM or packet processing equipment.

Family migration

The DS3161/DS3162/DS3163/DS3164 family is designed for one to four ports on a compatible board platform, subject to full design verification.

Feature Summary

ATM and HDLC paths

Maps ATM cells and/or HDLC packets into DS3/E3 digital streams and extracts them on receive.

Line framing

Supports DS3 M23 or C-bit and E3 G.751 or G.832 framing modes identified by Maxim.

Selectable bus width

System interface options include 8-, 16- or 32-bit bus widths for the documented UTOPIA/POS-PHY modes.

Clock-rate adaptation

Manufacturer documentation describes clock-rate adapter features; verify mode-specific clock requirements.

Package & Footprint

Maxim's exact ordering table specifies 400-ball TE-PBGA, 27 mm × 27 mm, 1.27 mm ball pitch for the unsuffixed DS3162. LCDChip's existing package field is 400-BBGA; its established package register maps that catalog label to 400-BBGA.jpg. The catalog name does not replace the manufacturer's thermal-enhanced package drawing or ball assignment.

400-BBGA catalog package reference for DS3162
Catalog package reference: 400-BBGA
Mechanical checks
  • Confirm the 27 mm square body, 1.27 mm pitch and A1 orientation.
  • Compare all 400 ball assignments with the original board layout.
  • Review the central thermal-ground-ball connection and assembly guidance.

The expected catalog JPG is absent locally and returns HTTP 404 on the production site. Restore and visually inspect it before publication.

Pin Functions

These are functional groups from the manufacturer documentation, not a replacement for the 400-ball map. The exact port number, multiplexed function and clock mode determine the active signal on many balls.

DS3/E3 digital line side

Per-port receive and transmit data, clocks, framing and overhead signals.

UTOPIA / POS-PHY system side

Configurable cell or packet bus data, control and clock signals.

Microprocessor control

Address, data, read/write, chip-select, ready and interrupt functions configure and monitor the device.

Power, ground and test

Supply, ground, clock and JTAG connections follow the full data-sheet ball assignment and board requirements.

Key Specifications

Exact modelDS3162
Manufacturer lineageMaxim Integrated; documentation hosted by Analog Devices
FunctionDual ATM/packet PHY with DS3/E3 framing
Number of portsTwo, independently configurable
Digital line modesDS3, E3 and supported clear-channel modes
Traffic formatsATM cells and HDLC packets
System-side interfacesUTOPIA L2/L3, POS-PHY L2/L3 or SPI-3 modes
Bus widths8, 16 or 32 bits, mode-dependent
Operating temperature0°C to +70°C for unsuffixed DS3162
Manufacturer package400-ball TE-PBGA, 27 × 27 mm, 1.27 mm pitch
Catalog package400-BBGA

Consult the complete Rev. 3 data sheet and applicable errata for electrical limits, clocks, interface timing and detailed register behavior.

Replacement Considerations

The DS3161, DS3163 and DS3164 provide one, three and four ports respectively; their family-level pin compatibility does not make them automatically equivalent to a two-port DS3162 in a populated board. Check port wiring, pin multiplexing, bus mode, framing configuration, clocks, register initialization, firmware assumptions and device revision. DS3162N is a different temperature-grade ordering code. Confirm any substitution through board-level tests and manufacturer documentation.

No internal alternative-product link is asserted without an exact LCDChip API catalog match and engineering verification.

Manufacturer Information

Analog Devices hosts the original Maxim Integrated DS3161–DS3164 Rev. 3 data sheet and the DS3162 product page. The document provides exact DS3162 ordering information, dual-port architecture, bus and framing features, 400-ball TE-PBGA drawing and extensive register descriptions. Review the manufacturer's errata for the revision installed in the target system.

Applications

Access concentrators

Dual-port DS3/E3 cell or packet termination in established systems.

Digital cross-connects

Framed transport integration with a system-side processing bus.

Routers and switches

Telecom uplink designs using supported ATM or HDLC paths.

Test equipment

Evaluation and maintenance of DS3/E3 transport interfaces.

Quality & Authenticity

Verify the exact DS3162 marking rather than DS3162N or another port-count member. Confirm manufacturer lot traceability, package condition, moisture handling and the target board's installed revision. The absent catalog image does not authenticate the physical part or demonstrate mechanical fit.

FAQ

How many line ports does DS3162 have?

Two independently configurable ports.

Does it handle both ATM cells and packets?

Yes. The data sheet describes ATM-cell and HDLC-packet mapping and demapping.

Which package is specified?

A 400-ball thermally enhanced PBGA, 27 mm square with 1.27 mm pitch.

Is DS3162N identical?

No. The N suffix denotes the -40°C to +85°C ordering option; verify the complete design requirements.

Engineering Notice

Validate external line-interface hardware, DS3/E3 framing, system-bus timing, clocks, register programming, package thermal-ground connections and board assembly against the complete Maxim data sheet and revision-specific errata. Restore and verify the production 400-BBGA JPG before the page is published.

DS3162 Information

  • Specifications
  • Tags
Product attributes
Attribute value
Manufacturer:
Analog Devices Inc./Maxim Integrated
Series:
-
Package/Case:
400-BBGA
Packaging:
Bulk
Product Status:
Obsolete
Programmable:
Not Verified
Type:
ATM/Packet PHYs
Applications:
-
Mounting Type:
Surface Mount
Supplier Device Package:
400-TE-PBGA (27x27)
Grade:
-
Qualification:
-
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