Analog Devices Inc./Maxim Integrated DS28E39Q+T

The DS28E39 combines a ChipDNA PUF, ECC-P256 cryptographic engine, true-random-number generator and protected EEPROM for challenge-response authentication over a 1-Wire connection. ChipDNA-derived material protects stored data and can, under user control, provide the ECDSA private key. A factory-programmed 64-bit ROM ID identifies the device on the bus. Authentication can be used in both host-to-device and device-to-host system flows.

LCDChip registers 6-WDFN Exposed Pad. Analog Devices' exact ordering row specifies DS28E39Q+T as a six-pin 3 mm × 3 mm TDFN-EP on tape and reel. The exposed paddle is soldered evenly to the board ground plane. Check the controlled footprint and pin-one orientation.

Layout checks

• Provide the specified external CEXT capacitor and 1-Wire pullup.
• Connect the exposed pad to the ground plane as directed.
• Confirm controlled TDFN-EP dimensions before PCB release.

The expected local JPG is absent and the production URL returns HTTP 404. Keep this draft unpublished until the correct image is restored and inspected.

The manufacturer's DS28E39Q+ TDFN pin table assigns pins 1, 4 and 5 as no-connect; pin 2 as 1-Wire IO; pin 3 as ground; and pin 6 as CEXT, the external-capacitor input. Solder the exposed pad to the ground plane for proper operation. Design the IO pullup and CEXT network from the electrical table rather than treating the capacitor pin as a general-purpose I/O.

Bus-speed descriptions differ within the public document; confirm timing against the controlled current revision and host implementation before design release.

Other ECDSA authenticators can differ in PUF behavior, key provisioning, certificate format, 1-Wire command set, EEPROM map, external-power requirements and footprint. Do not assume compatibility from ECC-P256 or a six-pin package alone. No unverified internal alternative is linked.

Analog Devices' DS28E39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection, public data sheet Rev. 0, supplies the exact Q+T ordering information, TDFN pin functions, electrical requirements and high-level security features. The separate Security User Guide is required for detailed commands.

Check package marking, traceability, TDFN geometry and unique ROM ID. Validate PUF-backed key behavior, host signature verification, protected-memory access and optional counter semantics. Test the 1-Wire power and timing network across the specified temperature range.

Obtain controlled security-command documentation, confirm timing and strong-pullup requirements, review key/certificate provisioning, and verify the exposed-pad footprint. Restore and inspect the live package JPG before formal publication.