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The Analog Devices / Maxim Integrated DS24L65P+T combines a SHA-256 coprocessor and a 1-Wire master in a six-pin TSOC surface-mount package.
Technical details are based on the manufacturer's DS24L65 abridged datasheet, Rev. 1.
The DS24L65 helps an I2C host authenticate compatible 1-Wire SHA-256 slave devices. It integrates the cryptographic engine, two user EEPROM pages, a configurable 1-Wire master, and protocol conversion so the host does not have to generate time-critical 1-Wire waveforms. The P+T ordering code specifies the lead-free six-pin TSOC form supplied on tape and reel.
SHA-256 hardware supports symmetric-key, bidirectional authentication designs.
On-chip 1-Wire timing reduces host software timing demands.
Active/passive pullup selection and strong pullup support attached devices.
Six-pin TSOC packaging suits compact controlled-access assemblies.
The manufacturer's order table identifies DS24L65P+T as a six-pin TSOC, package code D6+1. The catalog describes this as 6-SMD, J-Lead; use the manufacturer's TSOC outline and land-pattern drawings to verify the exact footprint. The T suffix denotes tape-and-reel supply, not a different electrical function.

The package illustration is indicative; mechanical design must follow the manufacturer's drawing.
Ground reference.
1-Wire line driver and sense input.
Power-supply input.
Active-low sleep and reset control.
I2C serial data; external pullup required.
I2C serial clock; external pullup required.
| Manufacturer | Analog Devices / Maxim Integrated |
|---|---|
| Order code | DS24L65P+T |
| Function | SHA-256 coprocessor and 1-Wire master |
| Package | Six-pin TSOC, D6+1; catalog 6-SMD J-Lead |
| Supply voltage | 1.71 to 1.89 V |
| Nominal I2C pullup voltage | 1.8 V ±5% |
| Operating temperature | −40 to +85 °C |
| Host interface | I2C standard or fast mode |
| I2C clock frequency | Up to 400 kHz |
| Downstream interface | 1-Wire master, standard or overdrive |
| User EEPROM | Two 32-byte pages |
| Authentication engine | SHA-256 |
| Sleep control | Active-low SLPZ input |
| 1-Wire line support | Selectable pullup and strong pullup |
| Ordering form | Lead-free, tape and reel |
Use the full manufacturer documentation for security provisioning and complete command behavior; the public datasheet is abridged.
DS24L65P+ is the corresponding non-tape-and-reel order form in the same six-pin TSOC family. For other devices, compare supply voltage, I2C command map, 1-Wire timing, authentication protocol, memory protection, package code, and pinout before substitution. No unverified internal product link is provided.
Analog Devices hosts the Maxim Integrated DS24L65 Rev. 1 abridged datasheet. Its ordering table explicitly lists DS24L65P+T as a −40 to +85 °C six-pin TSOC device and defines T as tape and reel.
Authenticate a compatible 1-Wire slave in a host-managed product.
Gate selected features using a provisioned authentication scheme.
Offload time-critical 1-Wire waveforms from an I2C host.
Use controlled memory and cryptographic functions in an embedded system.
Confirm the exact DS24L65P+T marking, six-pin TSOC package, and lot traceability. Protect secret provisioning and validate host-to-slave authentication with the actual system hardware.
It denotes tape-and-reel ordering; the datasheet lists the same six-pin TSOC package for P+ and P+T.
No. It is the host-side coprocessor and 1-Wire master; a compatible slave is separate.
The specified VCC operating range is 1.71 to 1.89 V.
Confirm the TSOC footprint and pin orientation, I2C and 1-Wire pullup networks, supply conditions, sleep control, security provisioning, and command behavior against the manufacturer documentation. The public datasheet is abridged and does not disclose every implementation detail.
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