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The Analog Devices / Maxim Integrated DS2476BQ+T is an ECC-P256 and SHA-256 secure coprocessor with an I2C host interface, two configurable open-drain outputs and a 6-WDFN Exposed Pad package (manufacturer designation: 6-pin TDFN-EP).
Select the complete BQ+T ordering code when checking electrical limits, package outline and tape-and-reel delivery. Technical values below refer to the manufacturer's DS2476B variant.
DS2476BQ+T provides hardware-assisted ECDSA signature generation and verification, ECDH, SHA-256/HMAC operations and secure nonvolatile storage for authentication systems. A host communicates over I2C. The device can act as a coprocessor companion to a compatible secure authenticator, but the system's key provisioning and certificate policy must be designed separately.
Hardware ECC-P256 supports ECDSA signature operations and ECDH key agreement.
SHA-256 and HMAC support authenticated transactions and firmware-security workflows.
A factory-programmed, unalterable 64-bit ROM identifier can participate in cryptographic operations.
I2C control, two open-drain GPIO pins and a compact exposed-pad package aid board integration.
ECC-P256, ECDSA, ECDH and SHA-256/HMAC.
8 Kbits of EEPROM for user data, keys and certificates.
True random-number source, decrement-only counter and two configurable GPIO pins.
DS2476BQ+T: DS2476B variant, 6-pin TDFN-EP, lead-free package, tape and reel.
The product record and package registry name is 6-WDFN Exposed Pad. The manufacturer's ordering table identifies DS2476BQ+T as a 6-pin TDFN-EP device; its package drawing describes a 3 mm × 3 mm body, package code T633+2, outline 21-0137 and land pattern 90-0058. Confirm the exact exposed-pad land pattern before PCB release.

The expected package JPG is not yet available on the production site. Image and publication require manual completion and verification.
Manufacturer top view of the 6-pin TDFN-EP package:
I2C clock; connect to VCC through a pull-up resistor.
I2C data; connect to VCC through a pull-up resistor.
Ground reference.
Open-drain general-purpose input/output.
Open-drain general-purpose input/output.
Supply voltage.
Solder evenly to the ground plane as directed in the package information.
Pin names and numbers follow the manufacturer's DS2476 abridged data sheet, Rev. 3.
| Device function | Secure ECC and SHA-256 coprocessor |
|---|---|
| Supply, DS2476B | 2.2 V minimum; 3.3 V typical; 3.63 V maximum |
| Operating temperature | -40°C to +85°C |
| Host interface | I2C; DS2476B SCL up to 1 MHz under specified timing |
| Cryptographic functions | ECC-P256 ECDSA / ECDH; SHA-256 / HMAC |
| EEPROM | 8 Kbits |
| EEPROM write endurance | 100,000 cycles, data-sheet specification |
| EEPROM data retention | 10 years at +85°C, data-sheet specification |
| GPIO | Two configurable open-drain pins, PIOA and PIOB |
| ROM identifier | Factory-programmed 64-bit ID |
| Package | 6-pin TDFN-EP, 3 mm × 3 mm; product record: 6-WDFN Exposed Pad |
| Ordering suffix | + lead-free package; T tape and reel |
Electrical limits are stated for the DS2476B. Apply the manufacturer's operating conditions and design notes when using any numerical limit; absolute-maximum ratings are not operating targets.
DS2476Q+T is listed in the same manufacturer's ordering table, but the non-B variant has different supply and I2C timing limits. It is a comparison candidate, not a confirmed drop-in replacement. Compare the complete order code, package code, power rail, I2C timing, GPIO behavior, provisioning and security requirements before considering any change. No unverified LCDChip internal product link is provided.
DS2476BQ+T is documented by Analog Devices under the Maxim Integrated DeepCover product family. Use the manufacturer's current controlled documentation, package drawings and revision notices when qualifying hardware or firmware.
Verify genuine peripherals in a host-controlled design.
Support device identity and protected key operations.
Use authenticated operations as part of a reviewed boot policy.
Store system secrets and certificates under a defined provisioning process.
Check the full order code, package marking, lot traceability and manufacturer documentation during receiving inspection. Cryptographic assurance also depends on secure key injection, host software and system-level threat analysis; the component alone does not certify an end product.
The B variant has different specified supply and I2C timing limits. Compare the manufacturer's variant-specific tables before substitution.
Yes. The manufacturer's 6-pin TDFN-EP pin description directs that the exposed pad be soldered evenly to the board ground plane.
No. The host must implement the I2C command flow and an appropriate security, key-provisioning and certificate policy.
Confirm the final schematic, pin orientation, package outline, electrical conditions and security workflow against the latest manufacturer-controlled data before production. The package illustration is pending; this detail must remain unpublished until the production JPG is available and visually verified.
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