Analog Devices Inc./Maxim Integrated DS1610S

The DS1610 monitors its 5 V input supply, controls power to attached SRAM, and gates chip-enable and write-enable signals to protect data when the supply leaves tolerance. When DIS is high, four address inputs allow programmed write protection of selected memory partitions; with DIS grounded, the SOIC device functions in a DS1210-like nonvolatile-controller mode. This is a controller for external RAM, not an integrated SRAM or a stand-alone real-time clock.

• Converts external CMOS SRAM into battery-backed nonvolatile memory.
• Protects all memory on a power-fail event and can protect selected blocks during normal supply operation.
• Automatically chooses an available battery source; two battery inputs support redundancy.
• Provides a power-fail output and power-up battery-status check.
• SOIC version can be configured for DS1210-style operation when DIS is grounded.

The controller routes the higher available supply to the RAM power output, inhibits CEO and WEO after a supply fault, and preserves an in-progress memory cycle within the data-sheet timing limits. TOL selects a nominal 5% or 10% power-fail threshold. In partition mode, a defined sequence of 20 read cycles followed by four register-loading read cycles programs write protection for as many as 16 address-selected partitions. This procedure is specialized; implement it from the original timing table, not from this overview alone.

The local catalog identifies a 16-SOIC with a nominal 0.295-inch (7.50 mm) body width. The original Dallas mechanical page shows a 16-pin 300-mil SOIC, and the exact-code Rochester listing calls DS1610S a 16-pin SOP. The generic local 16-SOIC registry entry has previously been identified as narrow-body; a dedicated 16-SOIC-Wide mapping requires confirmation. The matching local JPG is absent.

Assembly checks

• Confirm the 300-mil outline against the controlled Dallas drawing.
• Check pin one, 1.27 mm lead pitch and PCB land pattern.
• Review solderability, ESD control and lot markings before assembly.

The data sheet assigns VCCI to input power, VCCO to the RAM supply, VBAT1/VBAT2 to battery inputs, CEI/CEO and WEI/WEO to the protected memory-control paths, AW-AZ to partition addressing, TOL to threshold selection, DIS to partition-mode selection and PFO to power-fail indication. Use the manufacturer's pin-number diagram and electrical tables to wire the 16-pin device; package equivalence alone does not prove circuit interchangeability.

Electrical limits depend on operating mode and test conditions. The battery-backup current figure is a load limit, not the controller's own battery drain. Verify all AC timing against the original data sheet.

The local database contains DS1210S, which the Dallas data sheet describes as SOIC pin-compatible when the DS1610S DIS pin is grounded. That operating mode removes the DS1610's partition-programming behavior; it is not a universal replacement. The database also contains DS1610 without a verified package mapping. Any substitution requires checks of package, pinout, memory-control behavior, power-fail thresholds, batteries and timing.

The original Dallas Semiconductor DS1610 Partitioned NV Controller data sheet provides the functional description, pin assignment, electrical limits, timing and 300-mil SOIC drawing. Analog Devices/Maxim is the successor manufacturer in the local catalog. Rochester identifies the exact DS1610S code as a Maxim 16-pin SOP product and marks its lifecycle obsolete. Controlled data-sheet and purchasing evidence should accompany any production approval.

• Battery-backed external SRAM in industrial controllers.
• Retention of configuration or calibration data during power interruption.
• Protected program or special-data partitions in legacy memory systems.

The local catalog lists 17,464 units at USD 26.41 with minimum quantity 11 and no tier prices. Rochester's exact-code listing also shows 17,464 units but quotes USD 26.00 for 25-99, USD 24.70 for 100-499, USD 23.40 for 500-999, USD 22.10 for 1,000-9,999 and USD 20.80 at 10,000+. The matching stock count is encouraging, but the local minimum and price ladder are not reconciled with the current seller quote. Local stock and pricing are left unchanged pending procurement review, including date, lot, condition and lead time.

Confirm the exact S-package drawing, pin mapping, power-fail sequence, partition-programming procedure and battery load. Resolve the wide-body SOIC registry entry and missing local JPG, and reconcile current authorized stock and tier pricing. Keep this page in manual review with noindex; do not publish until every required check passes.