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The Analog Devices AD9942BBCZ integrates two CCD analog front ends and a programmable Precision Timing core. It is supplied in a 100-ball 9 x 9 mm CSP_BGA package and is obsolete.
Each channel supports CCD signal conditioning at pixel rates up to 40 MHz. The device combines correlated double sampling, variable gain, optical-black clamping and 14-bit conversion with clock and reset-gate timing drivers. It was designed for dual-output imaging architectures, not as a standalone image sensor.
Each analog front end includes a correlated double sampler, 0 to 18 dB 9-bit VGA, optical-black clamp and ADC. The timing core drives RG_A/RG_B and H1A to H4A/H1B to H4B clock sets, including a four-phase H-clock mode. A six-wire serial interface programs both channels.
Analog Devices lists the exact AD9942BBCZ order code in a 100-ball CSP_BGA, 9 x 9 x 1.4 mm. The catalog describes a 100-LFBGA/CSPBGA. The local package register has a generic 100-LFBGA entry but does not by itself establish the 9 x 9 mm ball map; check the manufacturer's controlled footprint. Its registered JPG is absent.

Channel A uses CCDIN_A at A1, serial controls SL_A at B2, SDATA_A at C2 and SCK_A at D2, and reference balls REFT_A at C1 and REFB_A at D1. Channel B has corresponding CCDIN_B, serial and reference connections. H1 through H4 and RG outputs drive the CCD timing path. Follow the manufacturer's full 100-ball assignment for supplies, grounds, drivers and no-connects.
| Function | Dual-channel CCD signal processor |
|---|---|
| Exact order code | AD9942BBCZ |
| ADC resolution | 14 bits per channel |
| Maximum pixel rate | 40 MHz per channel |
| ADC rate | 40 MSPS |
| VGA range | 0 to 18 dB, 9-bit control |
| Timing resolution | Less than 550 ps |
| Serial interface | Six-wire programmable |
| Clock driver | 3 V horizontal and reset-gate outputs |
| Temperature range | -25 to +85 degrees C |
| Package | 100-ball CSP_BGA, 9 x 9 x 1.4 mm |
| Lifecycle | Obsolete |
Check the full manufacturer timing and electrical tables for limits and loading.
Analog Devices' discontinuance notice names ADDI7013BBCZ as a replacement candidate but explicitly says it is not pin-to-pin compatible. No database-verified drop-in alternative is linked. Redesign and verify timing, register configuration, clock drivers, power domains and the ball map before substitution.
Analog Devices publishes the AD9942 Rev. A data sheet and lists AD9942BBCZ as obsolete. Its product discontinuance notice identifies the non-pin-compatible replacement candidate. Use current manufacturer documents and equipment-specific requirements for repair decisions.
For this obsolete device, verify full markings, lot traceability, storage history, solder-ball condition and package dimensions. Public broker inventory is not a confirmed authorized live quotation. The catalog price and quantity remain unverified and must not be represented as current distributor terms.
Two, each supporting up to 40 MHz pixel rates.
Yes, horizontal and reset-gate drivers are integrated.
No. Analog Devices marks ADDI7013BBCZ as not pin-to-pin compatible.
No. The local 100-LFBGA JPG is absent and the exact ball-map match requires review.
Validate the CCD input network, clamp levels, ADC timing, serial control, supply sequencing and every ball assignment before board use. Missing package JPG, unresolved registry footprint details and unverified live authorized inventory and tier prices prohibit publication.
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