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AD9267BCPZ is the Analog Devices tray-order code for a dual continuous-time sigma-delta modulator with 10 MHz real or 20 MHz complex signal bandwidth. It uses a 64-lead, 9 mm by 9 mm LFCSP with an exposed pad.
Confirm the exact ordering code, lot marking and 64-lead package drawing before installation.
Each AD9267 channel combines a resistive analog input with a fifth-order continuous-time sigma-delta loop filter. The device uses 32-times oversampling and provides four-bit differential LVDS modulator data per channel at 640 MSPS. A differential data clock output assists the receiving logic in capturing data.
Dual paths support real-bandwidth or complex I/Q receiver applications.
The architecture covers 10 MHz real or 20 MHz complex bandwidth under stated conditions.
A differential clock input or on-chip integer-N PLL can provide the internal conversion clock.
The continuous-time loop filter attenuates out-of-band signals and aliases.
The SPI-compatible port controls operating features and register settings.
Each channel presents a four-bit differential LVDS data bus and overrange indication.
DCO differential outputs provide a timing reference for downstream capture logic.
The documented analog supply is 1.8 V; verify all supply and driver rails against the data sheet.
ADI specifies a 64-lead LFCSP, 9 mm by 9 mm, with an exposed paddle. The catalog case name is 64-VFQFN Exposed Pad, CSP. The local register contains only a broader 64-VFQFN Exposed Pad name, so the exact CSP-suffixed mapping requires review.

The exact registered JPG is missing. Do not approve the package illustration until it is verified.
The ADI Rev. 0 data sheet provides the numbered 64-lead pin configuration and function table. These groups summarize functions, not a substitute for that pin table.
VIN+A/VIN−A and VIN+B/VIN−B are the differential channel inputs; VREF and CFILT support reference and filtering.
CLK+/CLK− accept a differential clock; PLLMULT pins select multiplication and PLL_LOCKED indicates lock.
D0± through D3± for each channel carry LVDS data. DCO± and OR± provide clock and overrange signals.
CSB, SCLK, SDIO, RESET and PDWN pins govern configuration; AVDD, DVDD, DRVDD and CVDD have separate roles.
Pins marked DNC must not be connected; exposed pad pin 65 must be soldered to the analog-ground plane.
| Exact order code | AD9267BCPZ |
|---|---|
| Manufacturer | Analog Devices |
| Function | Dual continuous-time sigma-delta modulator |
| Signal bandwidth | 10 MHz real or 20 MHz complex |
| Modulator clock rate | 640 MSPS |
| Oversampling ratio | 32 times |
| Output interface | Four-bit LVDS per channel with differential DCO |
| SNR | 83 dB (85 dBFS) to 10 MHz input, stated condition |
| Noise figure | 15 dB, stated condition |
| Power | 416 mW, stated operating condition |
| Analog supply | 1.8 V |
| Package | 64-lead LFCSP, 9 mm by 9 mm, exposed pad |
| Specified temperature | −40 °C to +85 °C |
Performance figures describe specified test conditions; consult the data sheet for limits and full operating conditions.
AD9267BCPZRL7 is an ADI ordering option for reel packaging of the same device family, but purchasing format alone does not establish full lot or board equivalence. Any proposed electrical substitute must be checked for continuous-time architecture, bandwidth, clocking, LVDS data format, SPI setup, supply rails and the exact 64-lead footprint. No unverified internal alternative link is shown.
Analog Devices publishes the AD9267 product page, Rev. 0 data sheet and package resources. The exact BC PZ tray code appears in ADI's ordering table. The page lists the order code in production while the family heading says not recommended for new designs; procurement should confirm current orderability and lead time.
Baseband quadrature reception in the communication systems identified by ADI.
Quadrature sampling instruments requiring wide bandwidth and dynamic range.
Maintenance of qualified receiver boards using this exact device and footprint.
Bench evaluation of continuous-time sigma-delta conversion and LVDS capture.
Check the full marking, tray labeling, date and lot code, package dimensions, moisture handling and traceability before assembly. Verify the source and test evidence for any independent-distributor lot. This listing does not imply a current authorized-stock quote or a completed incoming inspection.
Two continuous-time sigma-delta modulator channels.
Four-bit differential LVDS data per channel at the modulator rate, plus a differential data clock.
ADI marks the family not recommended for new designs despite listing this order code in production.
No. The exact case-name registration and JPG remain pending review.
Keep this detail under review until the exact package registry entry and JPG, ADI lifecycle/orderability, supplied-lot identity and a current qualified stock/price quote are confirmed. Do not publish while any gate remains open.
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