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Harris Corporation 8406901RA

Part No.:
8406901RA
Manufacturer:
Harris Corporation
Category:
Specialized ICs
Package:
20-DIP (0.300", 7.62mm)
Description:
IC BUS CONTROLLER 20CERDIP
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Product Details

8406901RA - Military-Grade CMOS Bus Controller

The 8406901RA is a Harris/Intersil 82C88-family CMOS bus controller in a 20-lead CERDIP package, qualified for harsh-environment systems and designed to generate command and control timing for 80C86/80C88, 8086/8088, 8089, and 80186/80188 processor buses.

Identity, package, temperature range, qualification, pin functions, and electrical characteristics were checked against the Renesas-controlled 8406901RA product record and 82C88 datasheet, revision 3.00.

Overview

8406901RA decodes the processor status inputs S0, S1, and S2 and produces memory, I/O, interrupt-acknowledge, address-latch, and data-transceiver control signals. The device supports both system-bus and I/O-bus operating modes, allowing the command outputs to be coordinated with external arbitration or used for a dedicated peripheral bus.

Use the IOB strap, AEN arbitration input, and CEN command-enable input exactly as defined for the intended bus topology. Advanced write outputs are provided to begin write control earlier in the machine cycle and can help avoid unnecessary wait states when the surrounding timing permits.

Key Advantages

Complete Bus Command Set

Generates memory read/write, I/O read/write, advanced write, interrupt acknowledge, latch-enable, and transceiver-control signals.

Legacy Processor Support

Designed for 80C86/80C88, 8086/8088, 8089, and 80186/80188 bus architectures.

Low-Power CMOS

Scaled SAJI IV CMOS construction combines static operation with bipolar-compatible output drive.

Military Qualification

The exact 8406901RA option is specified for -55°C to +125°C and QML Class Q / MIL-STD-883 flow.

Feature Summary

  • Compatible with the bipolar 8288 function
  • Three-state command outputs
  • Advanced commands for multi-master buses
  • Single 5 V supply
  • System-bus and I/O-bus modes
  • Active-low memory and I/O command outputs
  • Dedicated DEN and DT/R transceiver controls
  • 20-lead ceramic dual-in-line construction

Package & Footprint

The exact Renesas-controlled product record identifies 8406901RA as a 20-lead CERDIP, package code FBT, with a 2.54 mm lead pitch. LCDChip registers this footprint under the canonical 20-DIP package entry.

8406901RA 20-lead CERDIP package footprint
20-DIP
Layout checks
  • Confirm the 20-lead, 0.300-inch DIP land pattern and 2.54 mm pitch.
  • Observe the pin-1 indicator and top-view numbering before assembly.
  • Place a 0.1 µF decoupling capacitor between VCC pin 20 and GND pin 10 near the device.
  • Verify socket, lead-form, and ceramic-package height requirements.

The production JPG was checked at the registered public path and returned a valid JPEG response.

Pin Functions

The 20-lead CERDIP top-view pinout is defined in the 82C88 datasheet.

1 IOBSelects I/O-bus mode when high and system-bus mode when low.
2 CLKCMOS-compatible timing input from the system clock generator.
3, 19, 18 S1, S0, S2Processor status inputs decoded to generate command and control outputs.
4 DT/RSets external data-transceiver direction: high for transmit and low for receive.
5 ALEActive-high address-latch enable; latching occurs on its falling transition.
6 AENActive-low address-enable/arbitration input for command-output control.
7 MRDC, 8 AMWC, 9 MWTCActive-low memory read, advanced memory write, and memory write commands.
10 GND, 20 VCCGround and +5 V supply connections.
11 IOWC, 12 AIOWC, 13 IORCActive-low I/O write, advanced I/O write, and I/O read commands.
14 INTAActive-low interrupt-acknowledge command.
15 CEN, 16 DENCommand enable input and active-high data-transceiver enable output.
17 MCE/PDENMaster cascade enable in system-bus mode or peripheral data enable in I/O-bus mode.

Signal polarity and timing must be checked against the processor mode and bus-arbitration design; the grouped cards above do not replace the complete timing diagrams.

Key Specifications

Device functionCMOS bus controller
Supply voltage5 V nominal
Operating temperature-55°C to +125°C
Package20-lead CERDIP, Renesas package code FBT
Lead pitch2.54 mm
Package dimensionsApproximately 24.64 mm × 7.32 mm
QualificationQML Class Q; MIL-STD-883 flow
Standby supply current10 µA maximum
Operating supply current1 mA/MHz maximum
Processor compatibility80C86/80C88, 8086/8088, 8089, 80186/80188 families
Command outputsThree-state memory, I/O, advanced-write, and interrupt-acknowledge outputs

Electrical limits apply under the conditions in the Renesas 82C88 datasheet. Confirm clock rate, loading, and timing margins for the selected processor configuration.

Replacement Considerations

Do not substitute solely on the 82C88 function name. The CP82C88Z is a 20-lead PDIP commercial-temperature option that the controlled datasheet marks as no longer supported, so its material, qualification, temperature range, and lifecycle differ from 8406901RA. The MR82C88/B is a military-temperature 20-pad CLCC option with a different footprint and is also marked no longer supported. Verify pinout, package, temperature grade, qualification flow, timing, and lifecycle before considering either device.

Manufacturer Information

8406901RA is a legacy Harris/Intersil orderable device now documented by Renesas Electronics. The exact Renesas product record lists the part as active and identifies the 20-lead CERDIP package, military qualification, and -55°C to +125°C operating range.

Applications

Legacy Processor Boards

Command generation for 80C86/80C88 and 8086/8088-based computing or control assemblies.

Harsh-Environment Systems

Military-temperature bus-control designs requiring QML Class Q / MIL-STD-883 processing.

Multi-Master Buses

Systems that coordinate shared memory and I/O command timing with external arbitration.

Maintenance and Retrofit

Form-fit-function assessment for established 82C88-based equipment, subject to lot and qualification review.

Quality & Authenticity

For traceable procurement, compare the complete 8406901RA ordering code, package style, top marking, date and lot codes, and accompanying documentation. The controlled product record lists a non-lead-free, hot-solder-dip CERDIP construction and QML Class Q qualification; acceptance criteria should be matched to the project drawing and incoming-inspection plan.

FAQ

What does the 8406901RA do?

It decodes processor status inputs and generates memory, I/O, interrupt, address-latch, and data-transceiver control signals for compatible x86-family buses.

What package does this exact part use?

Renesas identifies 8406901RA as a 20-lead CERDIP with a 2.54 mm lead pitch; LCDChip maps it to the registered 20-DIP footprint image.

Is it suitable for military-temperature operation?

The exact product record specifies -55°C to +125°C, QML Class Q, and MIL-STD-883 flow.

Can CP82C88Z replace it directly?

Not without engineering review. CP82C88Z uses a PDIP package and commercial temperature range and is listed as no longer supported in the controlled datasheet.

Engineering Notice

Confirm the complete ordering code, ceramic package, qualification flow, bus mode, processor clock, command timing, output loading, and arbitration behavior against the latest controlled documentation before release. Related 82C88 variants can differ in package, temperature grade, lifecycle, and qualification and must not be treated as unconditional drop-in replacements.

8406901RA Information

  • Specifications
  • Tags
Product attributes
Attribute value
Manufacturer:
Harris Corporation
Series:
-
Package/Case:
20-DIP (0.300", 7.62mm)
Packaging:
Bulk
Product Status:
Active
Programmable:
Not Verified
Type:
Bus Controller
Applications:
-
Mounting Type:
Through Hole
Supplier Device Package:
20-CERDIP
Grade:
-
Qualification:
-
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