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Harris military-temperature bus controller for 80C86/80C88-family processor systems, supplied in a 20-pad ceramic leadless chip carrier.
Technical description checked against the Harris 82C88 datasheet. Confirm the exact device marking and package drawing before integration.
The MR82C88/B belongs to the Harris 82C88 high-performance CMOS bus-controller family. It decodes processor status and generates command and control signals for memory, I/O, and interrupt-acknowledge bus cycles. The family is designed for systems based on the 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188.
Generates memory and I/O command strobes from processor status inputs.
Harris CMOS design intended for processor support logic in legacy systems.
Provides address-latch, data-enable, and data-direction control alongside read/write commands.
The MR82C88/B ordering entry specifies an operating temperature range of -55 to +125 degrees Celsius.
S0, S1, and S2 indicate the processor bus-cycle type.
MRDC, AMWC, and MWTC support memory read and write operations.
IORC, AIOWC, and IOWC support peripheral read and write operations.
INTA, DEN, and DT/R coordinate interrupt acknowledgement and external data-bus devices.
The original Harris ordering table lists MR82C88/B as a 20-pad CLCC device with package drawing J20.A. The product database records its package as 20-CLCC. This is a ceramic leadless chip carrier, not a through-hole DIP.

The package JPG is presently unavailable on the production site; this draft must not be published until that asset and its rendering are verified.
The 20-pad CLCC pin diagram includes the following signal groups:
S0, S1, S2, CLK, AEN, CEN, and IOB select and qualify bus cycles.
ALE latches address information; DEN enables the data path; DT/R sets data-flow direction.
MRDC, AMWC, MWTC, IORC, AIOWC, IOWC, and INTA drive external bus functions.
MCE/PDEN is a multiplexed control signal; VCC and GND provide power and return.
Consult the manufacturer top-view pin diagram for pad numbers and polarity before wiring. Signal names alone do not establish pin-to-pad placement.
| Manufacturer | Harris Corporation |
|---|---|
| Ordering code | MR82C88/B |
| Device family | 82C88 CMOS bus controller |
| Function | Processor bus command and control generation |
| Package | 20-pad ceramic leadless chip carrier (CLCC) |
| Package drawing | J20.A |
| Operating temperature | -55 to +125 degrees Celsius (ordering-table rating) |
| Supply class | Single nominal +5 V supply; verify operating limits in the datasheet |
| Status inputs | S0, S1, S2 |
| Memory commands | MRDC, AMWC, MWTC |
| I/O commands | IORC, AIOWC, IOWC |
| Other bus signals | ALE, DEN, DT/R, INTA, MCE/PDEN |
Values identify this ordering entry and family functions; timing limits depend on the applicable datasheet grade and system conditions.
Do not select a replacement by the 82C88 family name alone. Match the 20-pad CLCC footprint, pinout, military-temperature requirement, logic levels, command polarity, and bus timing. The manufacturer's stated 8288 functional compatibility does not by itself prove that another package or temperature grade is a drop-in replacement.
No internal substitute is linked here because an exact stocked product match and its package compatibility have not been verified.
The product record identifies Harris Corporation. The Harris-issued 82C88 datasheet provides the MR82C88/B ordering entry and 20-pad CLCC package designation. A successor-hosted copy of the 82C88 documentation is available from Renesas; consult its revision notes and the original Harris drawing when qualifying legacy hardware.
Bus command generation in 80C86/80C88-family designs.
Control strobes for external memory read and write cycles.
I/O command generation and interrupt-acknowledge coordination.
Identification of original bus-control logic in existing military-temperature equipment.
Confirm part marking, ceramic package construction, orientation, and traceability against the purchase and inspection requirements. Visual package similarity does not establish electrical equivalence or authenticity. Apply appropriate incoming inspection and functional testing to legacy components.
It decodes processor bus status and generates memory, I/O, interrupt, latch, and transceiver-control signals.
The Harris ordering table specifies a 20-pad CLCC, drawing J20.A.
The MR82C88/B ordering entry lists an operating range of -55 to +125 degrees Celsius; verify all other system requirements separately.
No direct replacement should be assumed. Package, pad assignment, temperature grade, and timing must be checked against the board design.
This page is a technical identification aid, not a substitute for the manufacturer datasheet. Verify the precise ordering code, package drawing, operating conditions, and timing before design-in or repair. The production package image is missing, so this draft remains under review and must not be published.
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