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Intersil HD9P6409-9 is a 1-Mbps CMOS Manchester encoder/decoder in a 20-lead wide SOIC (M20.3). The manufacturer's historical ordering table identifies this exact non-Z code; it must not be silently replaced with the later Pb-free -9Z variant.
Manufacturer technical reference: Intersil HD-6409 data sheet FN2951.3, October 2008. The original code was included in a subsequent Intersil end-of-life notice.
The HD-6409 converts nonreturn-to-zero serial data to Manchester II code and decodes received Manchester data back to NRZ. Converter mode supports a transmit/receive endpoint; repeater mode reconstructs incoming coded data using a recovered clock. A digital phase-locked loop provides receive timing. The device supplies coding and synchronization functions, not a complete communications protocol or isolated line interface.
Independent Manchester encoder and decoder functions on one device.
Digital PLL extracts a receive clock from valid Manchester input.
Converter and repeater modes cover endpoints and regenerated links.
The original Intersil ordering table explicitly lists HD9P6409-9 in SOIC.
Static to 1 Mbit/s in the manufacturer's HD-6409 family specification.
MS selects converter or repeater behavior; consult the truth and timing descriptions.
On-chip oscillator option or external reference clock through IX; SS selects 16x or 32x timing.
NVM and sync-related signals assist supervision of decoded serial data.
The Intersil FN2951.3 ordering table assigns exact HD9P6409-9 to a 20-lead SOIC, package drawing M20.3. The catalog's 0.295-inch (7.50-mm) wide 20-SOIC entry normalizes to the registered 20-SOIC package. The non-Z and Z codes may differ in lead finish and Pb-free handling; do not substitute one procurement code for the other without a controlled assessment.

The 20-SOIC package is registered locally, but its JPG is absent; retain manual review.
The Intersil 20-lead top view assigns BZI/BOI/UDI to decoder inputs at pins 1-3; SD/CDS at pin 4 is serial data input in converter mode or sync-status output in repeater mode. SDO, SRST, NVM, DCLK and RST occupy pins 5-9; GND is pin 10. CO, IX, OX, MS, CTS, ECLK and SS occupy pins 11-17. BZO and BOO are encoder outputs at pins 18-19; VCC is pin 20.
BZI/BOI bipolar inputs and UDI unipolar input; select only the intended input configuration.
SD/CDS, SDO, SRST, NVM, DCLK and reset functions.
CO, IX, OX, MS, CTS, ECLK and SS.
BZO, BOO and +5 V VCC; GND is pin 10.
Check polarity, mode-dependent behavior and decoupling against the data sheet before layout.
| Exact order code | HD9P6409-9 (non-Z) |
|---|---|
| Original manufacturer | Intersil; HD-6409 family |
| Function | CMOS Manchester encoder/decoder |
| Maximum serial data rate | 1 Mbit/s family grade |
| Operating modes | Converter and repeater |
| Receive clock recovery | Digital phase-locked loop |
| Reference-clock ratio | 16x or 32x selected by SS |
| Supply | +5 V nominal; consult manufacturer electrical limits |
| Operating temperature | -40 to +85 C per exact ordering row |
| Package | 20-lead SOIC, M20.3; normalized 20-SOIC |
| Typical operating power | 50 mW at +5 V under manufacturer-stated family conditions; not a maximum |
| Life-cycle | Original non-Z code listed in Intersil 2015 end-of-life notice |
Observe data-sheet test conditions and distinguish typical values from guaranteed limits.
No LCDChip internal alternate has been verified or linked. The later HD9P6409-9Z is a Pb-free SOIC order code in the manufacturer's family table, but it is not an automatic procurement or process substitution for non-Z stock. Compare package drawing, lead finish, solder profile, timing, operating grade, markings and lifecycle before any change. The HD3-6409 PDIP family member requires a different board footprint.
Intersil's October 2008 data sheet FN2951.3 explicitly lists HD9P6409-9 and its M20.3 SOIC package. The manufacturer's product-life-cycle notice PLC15033 later lists the original code for withdrawal and obsolescence. Renesas' present HD-6409 literature highlights Pb-free -9Z ordering; that current suffix must not be mistaken for the catalog's exact non-Z product.
Manchester coding for synchronous point-to-point data transfer.
Reconstruct coded signals using recovered clock timing.
Historical system designs using Manchester's transition-based timing.
Like-for-like replacement after marking, finish and package checks.
Confirm traceable non-Z lot markings, date code, package drawing M20.3, lead condition and storage history. The original code's end-of-life notice makes broker listings particularly sensitive to lot age and authenticity. Catalog stock and base price are separate fields; current exact-code listings report divergent stock and quantity prices, so obtain a dated authorized quote before commercial changes or release.
It converts NRZ serial data to Manchester II and decodes received Manchester back to NRZ.
No. The manufacturer's table distinguishes the Pb-free Z suffix from the non-Z code.
The exact Intersil ordering row specifies 20-lead SOIC M20.3; inspect the supplied lot and footprint.
No. The required 20-SOIC JPG and exact current price/stock reconciliation remain outstanding.
Keep HD9P6409-9 under manual review. Restore the registered 20-SOIC JPG, verify the lot's non-Z marking and lead finish, reconcile authorized exact-part inventory and tier pricing, and repeat hash, package and rendered-page checks before any human publication decision. A Pb-free suffix change is not approved by this page.
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