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National Semiconductor DP83222V
- Part No.:
- DP83222V
- Manufacturer:
- National Semiconductor
- Category:
- Specialized ICs
- Package:
- 28-LCC (J-Lead)
- Description:
- IC STREAM CIPHER SCRAMBLE 28PLCC
- Quantity:
Unit Price:$0
Ext Price:$0
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Product Details
DP83222V - CYCLONE Twisted-Pair FDDI Stream Cipher Device
National Semiconductor's DP83222V scrambles and descrambles the serial data stream between an FDDI physical-layer device and a twisted-pair PMD transceiver. The V ordering code is specified in the original datasheet for a 28-pin plastic leaded chip carrier.
Source: National Semiconductor DP83222 datasheet, August 1994, order number DP83222V. Confirm legacy-system compatibility and present-day supply before procurement.
Overview
The DP83222 CYCLONE is a synchronous FDDI stream-cipher scrambler and descrambler for twisted-pair PMD links. It accepts transmit data and a 125 MHz transmit clock from the PHY side and delivers scrambled data to the PMD. In the receive direction it uses PMD data and the recovered 125 MHz clock to reconstruct a time-aligned, descrambled data stream for the PHY.
Key Advantages
Twisted-pair FDDI interface
Designed to work directly with TP-PMD serial bit streams and the National Semiconductor FDDI chipset.
Reduced emissions
Data scrambling helps reduce EMI on unshielded copper media.
Receive synchronization
A sample-and-hold descrambler detects FDDI line states and aligns its 11-bit LFSR.
Configurable encoding
ENC0 and ENC1 select NRZ/NRZI combinations or transparent pass-through.
Feature Summary
Transmit scrambler
An 11-bit linear feedback shift register and XOR logic operate on NRZ-formatted PHY data.
Receive descrambler
Recognizes valid FDDI line states before holding synchronization and delivering reconstructed data.
Link supervision
Clock Detect and Signal Detect inputs return the receive cipher to sample mode when clock or medium signal is lost.
System integration
Provides differential 100K ECL data/clock paths and TTL-compatible encoding controls.
Package & Footprint
National's original datasheet names DP83222V as a 28-pin plastic leaded chip carrier, package number V28A. The catalog alias is 28-LCC (J-Lead), mapped by the local package registry to 28-LCC and 28-LCC.jpg. Verify the manufacturer's dimensions, J-lead land pattern and pin-one marking before layout.
- Match the V28A outline to the socket or PCB land pattern.
- Preserve differential-clock and differential-data routing symmetry.
- Provide the required 100K ECL terminations and supply decoupling.
The registered local package JPG is missing and must be supplied and reviewed before publication.
Pin Functions
The original datasheet's 28-pin PLCC table identifies the following signal groups. Confirm orientation and the complete pin drawing before generating a schematic symbol.
Transmit side
TXD+/- on pins 18/17 and TXC+/- on pins 13/14 receive differential PHY data and clock; SCO+/- on pins 19/20 provide scrambled PMD data.
Receive side
RXD+/- on pins 3/2 and RXC+/- on pins 5/6 accept PMD data and recovered clock; DSCO+/- on pins 27/26 and RXCO+/- on pins 24/25 return aligned data and clock.
Controls
ENC0 pin 9 and ENC1 pin 8 set encoding mode; CD pin 10 and SD pin 12 monitor receive clock and signal.
Power and returns
VCC pins 7/16/28, GND pins 1/4/11/15, ECLVCC pin 21, ECLGND pin 22 and EXTVCC pin 23 provide separate supply connections.
Key Specifications
| Ordering code | DP83222V |
|---|---|
| Original manufacturer | National Semiconductor |
| Function | CYCLONE twisted-pair FDDI stream-cipher scrambler/descrambler |
| Line signaling | 100 Mb/s FDDI over Category 5 UTP or Type 1 STP |
| Transmit and receive clocks | 125 MHz nominal synchronous clocks |
| Cipher structure | 11-bit linear feedback shift register |
| Data formats | Selectable NRZ, NRZI and transparent modes |
| Recommended VCC | 4.5 to 5.5 V |
| Operating temperature | 0 to 70 degrees C |
| Interface families | Differential 100K ECL data/clock; TTL-compatible CMOS control inputs |
| Package | 28-pin PLCC, National package number V28A; catalog alias 28-LCC (J-Lead) |
Electrical values are from the original National datasheet. Observe its supply, timing, termination and thermal conditions when checking a design.
Replacement Considerations
A replacement must match FDDI scrambling and line-state synchronization, 125 MHz timing, NRZ/NRZI selection, ECL signal levels, differential pinout, supply partitioning, package and legacy PHY/PMD interoperability. The companion DP83223 twisted-pair transceiver has a different function and is not a substitute for this cipher device.
No internal alternative-product link is shown because no electrically and mechanically verified replacement with a database URL was established.
Manufacturer Information
National Semiconductor published the DP83222 CYCLONE datasheet in 1994. Its last page explicitly lists DP83222V and package V28A. Confirm present lifecycle, authorized distribution and any Texas Instruments successor documentation before sourcing.
Applications
Legacy FDDI infrastructure
Twisted-pair PMD links between FDDI physical-layer and media transceiver devices.
UTP or STP media interfaces
100 Mb/s FDDI signaling over specified copper media.
Fiber-PMD replacement designs
Supports system designs that replace a fiber optic PMD with a twisted-pair PMD architecture.
Quality & Authenticity
Verify the DP83222V marking, V28A package, date/lot traceability and storage history for any legacy stock. The site's existing inventory and price are not a verified current distributor quotation; obtain an exact-part offer with quantity-break pricing before procurement.
FAQ
Is DP83222V a general encryption chip?
No. It is a line scrambler/descrambler for twisted-pair FDDI signaling and EMI control.
What clock does the device require?
The original datasheet specifies a 125 MHz transmit clock and corresponding receive clock for synchronous operation.
Can the DP83223 transceiver replace it?
No. DP83223 is a companion twisted-pair transceiver, not the DP83222 stream cipher.
Is the package image ready?
No. The registered 28-LCC JPG is missing locally.
Engineering Notice
Before board reuse or redesign, check the original National timing tables, FDDI line-state behavior, ECL terminations, separate supply connections and V28A package drawing. The missing package JPG and unverified present-day stock and tier prices prevent publication of this draft.
DP83222V Information
- Specifications
- Tags
- Product attributes
- Attribute value
- Manufacturer:
- National Semiconductor
- Series:
- CYCLONE™
- Package/Case:
- 28-LCC (J-Lead)
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Stream Cipher Scramble
- Applications:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.43x11.43)
- Grade:
- -
- Qualification:
- -
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