Analog Devices Inc. ADSP-1401JN

The ADSP-1401 selects the next address in a microcoded processor. It supports sequential execution, branches, subroutines, conditional tests and interrupt entry. Its 16-bit address port reaches a 64K-word microprogram space. A Look-Ahead pipeline supports address selection across the clock phases; timing must follow the J-grade switching table rather than the faster K-grade headline.

• 16-bit microcode addressing for legacy word-slice designs.
• Configurable on-chip RAM for stacks and indirect jump addresses.
• Prioritized, maskable interrupt control with internal event sources.
• Four decrementing event counters for loop control.
• Writable-control-store download support.

The manufacturer describes a 64-word RAM partitionable among subroutine stack, register stack and indirect jump storage. Ten interrupt vectors comprise eight user/external sources and two internally generated events. Address sources include the data port, program counter, interrupt vectors and stored jump addresses. The instruction set covers absolute, relative and indirect addressing, stack operations and conditional branches.

ADI lists the exact JN order code as a 48-pin plastic dual-in-line package, N-48A outline. The local package register calls it 48-DIP and expects the JPG below. Verify 0.600-inch body, row spacing, pin-one orientation and socket dimensions against N-48A before replacement.

Mechanical checks

• Compare N-48A package outline with the board socket.
• Check all 48 through-hole leads for damage and corrosion.
• Confirm package marking and date code.

The expected local 48-DIP JPG is not yet available.

The original ADI DIP pin-configuration table identifies D0-D15 as the bidirectional data port and Y0-Y15 as the microprogram address outputs. CLK is pin 41, FLAG pin 40, VDD pin 37 and GND pin 12. EXIR1 and EXIR2 are pins 10 and 11; EXIR3 and EXIR4 are pins 13 and 14. TTR on pin 15 supports trap, three-state and reset control. Verify each numbered connection against the N-48A drawing and the actual board revision.

Use the J-grade electrical table, loading assumptions and timing diagram for design margins; family feature headlines include faster grade values.

No database-verified LCDChip alternate is linked. ADSP-1401KN uses a different speed grade, ADSP-1401JD a ceramic DIP, and ADSP-1401JP a 52-lead PLCC. ADSP-1410 is a data-address generator, not a microprogram-sequencer replacement. Compare microcode, J-grade timing, reset and interrupt behavior, package, and temperature limits before any substitution.

Analog Devices' original DSP Products Data Book gives the exact ADSP-1401JN ordering entry, DIP pin configuration, functional description and J/K/S/T grade table. These archival primary documents establish historical specifications; a dated authorized supply quote and lot provenance require separate confirmation.

• Microcoded digital signal processors and array processors.
• Word-slice controller boards requiring conditional microcode branches.
• Legacy systems with prioritized interrupts and writable control stores.

Inspect ADI marking, JN suffix, date and lot codes, 48-pin plastic package and lead condition. Treat public distributor stock and price schedules as time-sensitive; obtain an exact-code, dated authorized quote before changing catalog commercial fields. Obsolete-device handling should include ESD protection and traceability.

Validate J-grade switching limits, control sequencing, external interrupt wiring, DIP footprint and actual lot identification against the original ADI documents. The missing package JPG and unreconciled current price terms block publication.