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Analog Devices' AD9801 integrates an 18 MSPS correlated double sampler, variable-gain amplifier, black-level clamp, voltage reference and 10-bit ADC for electronic-camera CCD signal chains in a 48-lead thin quad flat package.
ADI marks the AD9801 obsolete. The original Rev. 0 datasheet describes the base device and 48-pin TQFP; the exact JCSTRL packing suffix needs supplier confirmation.
The AD9801 processes a CCD pixel waveform through correlated double sampling, a variable-gain amplifier, black-level correction and a 10-bit converter. It provides the sampling clocks, input clamp and on-chip reference needed for a compact electronic-camera analog front end. Its parallel data outputs feed a downstream digital image processor.
CDS, gain, clamp and conversion are combined in one signal path.
CDS and the 10-bit ADC support rates up to 18 MSPS under specified conditions.
Clamping and black-level correction establish a stable CCD reference.
The analog, digital and output-driver domains operate from the specified +3 V supply range.
Parallel D0-D9 outputs deliver 10-bit conversion results with no missing codes guaranteed.
Reference and data samples are subtracted to reduce correlated CCD noise.
PGACONT1 and PGACONT2 provide coarse and fine gain adjustment.
Reference and bias blocks reduce the number of external analog functions.
ADI describes a 48-pin thin quad flatpack (TQFP) for the AD9801. The LCDChip record and local registry use 48-LQFP and map it to 48-LQFP.jpg. Confirm that the exact JCSTRL order code uses the manufacturer outline and check pin-one, lead pitch and body dimensions before PCB release.

The registered local package JPG is missing; do not publish until the image and footprint are reviewed.
The AD9801 Rev. 0 pin-function table groups the 48 leads as follows; use the full ADI top-view diagram for placement and polarity.
DIN and PIN are the CDS input connections; CCDBYP1 and CCDBYP2 are CCD bypass nodes requiring local capacitors.
SHP and SHD are the reference and data sample clocks; ADCCLK clocks the converter. CLPOB, CLPDM, PBLK and STBY control clamp, blanking and standby states.
PGACONT1 and PGACONT2 control coarse and fine gain. D0-D9 are the 10-bit parallel data outputs.
ACVDD, ADVDD, DVDD and DRVDD power separate domains; matching VSS pins are their returns. VRT, VRB and bias pins support the reference network.
Do not infer electrical connectivity from similar CCD processors; follow the exact AD9801 pin table and decoupling notes.
| Ordering code | AD9801JCST; exact packing suffix to be confirmed |
|---|---|
| Manufacturer | Analog Devices Inc. |
| Function | CCD analog signal processor for electronic cameras |
| ADC resolution | 10 bits; no missing codes guaranteed |
| Maximum sample rate | 18 MSPS under specified conditions |
| CDS pixel rate | Up to 18 MHz under specified conditions |
| Functional supply range | 3.00 to 3.50 V for ACVDD, ADVDD, DVDD and DRVDD |
| Typical normal power | 185 mW at the datasheet test conditions |
| PGA maximum gain | 31.5 dB under stated control conditions |
| Operating temperature | 0 to +70 degrees C |
| Manufacturer package | 48-lead TQFP; LCDChip registry 48-LQFP |
| Lifecycle | Obsolete according to ADI |
Specifications refer to the AD9801 Rev. 0 datasheet, primarily at 3.15 V supplies. Confirm the full JCSTRL ordering suffix and applicable lot documentation.
Any replacement must match CDS timing, CCD input range, PGA control, black-level loop, 10-bit output format, 18 MSPS throughput, +3 V supplies, 48-lead mechanical outline and host timing. A newer camera front end may need both hardware and firmware changes.
No internal alternative-product link is shown because no verified pin-, timing- and performance-compatible replacement with a confirmed LCDChip product URL was established.
Analog Devices published the AD9801 Rev. 0 datasheet for a 10-bit CCD processor and currently marks the base product obsolete. The document describes a 48-pin TQFP. Confirm the JCSTRL suffix, packaging format, original markings and supply chain with a qualified supplier.
CCD output conditioning and digitization for consumer imaging designs.
Real-time CCD pixel acquisition using CDS, gain and 10-bit conversion.
Replacement of the same verified order code in existing equipment.
For this obsolete device, verify the exact ordering code, package marking, lot traceability, storage and ESD handling. Public listings show differing stock figures and mostly RFQ or secondary prices; the existing catalog stock and price are not a confirmed current offer.
The AD9801 integrates a 10-bit ADC with parallel D0-D9 outputs.
The datasheet specifies operation up to 18 MSPS under its stated conditions.
The base AD9801 function is documented; confirm the complete JCSTRL suffix with a supplier.
No. The registered 48-LQFP.jpg is missing locally.
Before using this obsolete part, review CCD waveform levels, SHP/SHD and ADCCLK timing, black-pixel clamp sequencing, gain-control range, reference bypass, output loading and the exact 48-lead footprint. Missing package imagery and unverified exact-code pricing prevent publication.
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