Enabling Ultra-Scaled and Low-Power Electronics

Core Technical Advantages Over Traditional Silicon FETs

Two-dimensional transition metal dichalcogenides (2D TMDs)-based field-effect transistors (FETs) outperform traditional silicon (Si) FETs in terms of scaling potential, switching speed, and power consumption-critical for next-generation ultra-scaled and low-power electronic devices. According to the IEEE Electron Devices Society 2025 Technical Report, monolayer molybdenum disulfide (MoS₂), a typical 2D TMDs material, exhibits an electron mobility of 200 cm²/V·s at room temperature, and its atomic-level thickness (0.65 nm) enables channel lengths down to 1 nm without significant short-channel effects (SCEs), which plague Si FETs when scaled below 5 nm. Additionally, 2D TMDs FETs achieve a subthreshold swing (SS) of 65 mV/dec, approaching the theoretical limit (60 mV/dec at 300 K), and their off-state leakage current is 100 times lower than that of Si FETs, reducing static power consumption by 90%.

Key Material and Fabrication Breakthroughs

A U.S.-based research team announced a major breakthrough in 2D TMDs material quality in Q4 2025, published in Nature Electronics. By developing a chemical vapor deposition (CVD) process with a sapphire substrate patterned with graphene seeds, the team synthesized large-area (4-inch wafer scale) monolayer MoS₂ with a defect density of 1.2×10¹¹ cm⁻²-80% lower than conventional CVD-grown MoS₂ (6×10¹¹ cm⁻²). This improvement boosts the electron mobility of MoS₂ FETs to 350 cm²/V·s, making it comparable to polycrystalline Si FETs. The team also demonstrated that the large-area MoS₂ film exhibits uniform electrical properties, with a mobility variation of less than 5% across the entire wafer.

Meanwhile, a Chinese semiconductor firm developed a low-temperature atomic layer deposition (ALD) process for high-k dielectric integration with 2D TMDs. By using hafnium oxide (HfO₂) as the high-k dielectric and optimizing the ALD temperature to 150°C, the company achieved a dielectric constant of 25 and a leakage current density of 1×10⁻⁸ A/cm² at 1 V. This process solves the interface compatibility issue between high-k dielectrics and 2D TMDs, reducing the interface trap density to 5×10¹¹ cm⁻²·eV⁻¹-30% lower than the industry average. The resulting 2D TMDs FETs with HfO₂ dielectrics achieve a switching speed of 100 GHz, meeting the requirements of 6G high-frequency communication applications, according to the IEEE Transactions on Nanotechnology 2025 Technical Report.

Industry Application Scenarios

In the ultra-scaled integrated circuit (IC) sector, 2D TMDs FETs are being explored as a replacement for Si FETs in advanced technology nodes (3 nm and below). A leading semiconductor foundry announced a prototype 3 nm IC chip based on MoS₂ FETs, which has a transistor density of 200 million/cm²-40% higher than that of Si-based 3 nm ICs. The chip also exhibits a 50% reduction in power consumption, making it suitable for high-performance computing (HPC) and data center applications. For flexible electronics, a South Korean electronics manufacturer integrated WSe₂ (tungsten diselenide) FETs into a flexible display driver circuit, which can withstand 100,000 bending cycles (bending radius 1 mm) with less than 10% performance degradation.

In the 6G communication field, 2D TMDs FETs' high switching speed enables the development of ultra-high-frequency RF devices. A European telecom equipment firm developed a 6G RF amplifier based on MoS₂ FETs, which operates at 300 GHz with a gain of 15 dB and a power-added efficiency (PAE) of 25%-performance metrics that surpass Si-based RF amplifiers at the same frequency. Additionally, in quantum computing, 2D TMDs materials' spin-valley coupling properties make them promising for spin qubits. A U.S. quantum technology startup demonstrated a MoS₂-based spin qubit with a coherence time of 10 μs, which is 5 times longer than that of Si-based spin qubits, laying the foundation for scalable quantum computing.

Current Technical and Market Challenges

The commercialization of 2D TMDs-based FETs is hindered by three core challenges: large-area high-quality material synthesis, high fabrication costs, and poor contact resistance. Despite recent breakthroughs, large-area (8-inch and above) 2D TMDs films with uniform properties are still difficult to synthesize, and the yield of monolayer films is less than 60%. The fabrication process of 2D TMDs FETs requires expensive equipment (e.g., high-precision CVD systems, ALD tools), with a single-wafer processing cost that is 3 times higher than that of Si FETs.

Market-wise, global 2D TMDs FETs are still in the research and development stage, with no mass production yet. Major semiconductor companies such as Intel, TSMC, and Samsung are investing in 2D TMDs technology, but commercialization is not expected until 2030. Supply chain constraints also exist-key raw materials (e.g., high-purity molybdenum, sulfur) and specialized equipment are dominated by a few overseas suppliers, leading to a 14-week delivery cycle and a 35% cost premium. Additionally, there is a lack of unified international standards for 2D TMDs material and device performance testing, which hinders technology transfer and market acceptance.